Most integrated circuits (ICs) of sufficient complexity utilize a clock signal in order to synchronize different parts of the circuits. Typically, delivering a clock signal to different areas of the chip requires a metal grid, which provides a low amount of skew. A clock distribution network (i.e., clock tree) distributes the clock signal or signals from a common point to all elements of that chip that require it. Since function is vital to the operation of a synchronous system, special attention is typically directed to characteristics of these clock signals and the electrical networks used in the distribution of these clock signals. Presently, distances are manually measured between each control clock tree source and respective sink, where a tree is individually created based on reach-tables. Reach-tables include maximum distances for which a given repower circuit can drive on a specific wire-plane with respectively selected wire-code. Subsequently, the respective control clock tree sub-stage or sub-stages are logically implemented by hand with respective Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) code snippets.